| Syllabus: Introduction to Electronic Design Automation |
| August 5 |
Introduction and Motivation |
| Hour 1 |
Background, EDA industry challenges |
| Hour 2 |
Role of machine learning in EDA |
| Hour 3 |
Basics of algorithms and time complexity |
| Hour 4 |
Graph traversals: DFS and BFS, application to maze routing |
| Hour 5 |
Graph traversals: Topological search: application to static timing analysis |
| August 6 |
Physical design |
| Hour 1 |
Graph traversals: Topological search: application to static timing analysis |
| Hour 2 |
Partitioning: Kernighan-Lin and Fidduccia-Mattheyses algorithms |
| Hour 3 |
| Hour 4 |
| Hour 5 |
Floorplanning: slicing floorplans and sequence pairs |
| August 7 |
Physical design |
| Hour 1 |
Floorplanning: slicing floorplans and sequence pairs |
| Hour 2 |
| Hour 3 |
Placement |
| Hour 4 |
| Hour 5 |
| August 8 |
Making designs tolerant to process variations |
| Hour 1 |
Global routing: Steiner tree construction |
| Hour 2 |
Global routing: Simultaneous routing, congestion estimation, machine learning methods |
| Hour 3 |
| Hour 4 |
Static Timing Analysis |
| Hour 5 |
| August 9 |
Making designs tolerant to runtime variations |
| Hour 1 |
Timing analysis under variations: corners, statistical analysis |
| Hour 2 |
Lithography, multiple patterning, ML methods，conclusion |
| Hour 3 |
| Hour 4 |
| Hour 5 |
