Publications @ CADET Lab.

INVITED TALKS

[1] “Low Power Design for STT-MRAM based Last Level Cache”, University of Pisa, Italy, Inviter: Prof. Giuseppe Iannaccone, May 29, 2018. [slides]

[2] “Low Power and Reliable Design for Emerging Technologies”, University of Verona, Italy, Inviter: Prof. Franco Fummy (Program Chair of DATE 2019), Oct. 30, 2018. [slides]

[3] “Low Power and Reliable Design for Emerging Technologies”, Nanjing University of Aeronautics and Astronautics, Inviter: Prof. Weiqiang Liu, (Vice dean of EECS department), May 17, 2019. [slides]

[4] “Design for Testablility and Reliability of 3D Integrated Circuits, University of Electronic Science and Technology of China, Inviter: Prof. Letian Huang (School of Microelectronics), May 24, 2019. [slides]

[5] “Low Power and Reliable Design for Emerging Memory Technologies,” invited talk, IEEE 8th Non-Volatile Memory Systems and Applications Symposium, Hangzhou, China, Aug. 19, 2019. [slides]

BOOK CHAPTERS

[1] Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard,
Arnaud Virazel, Pascal Vivet, Marc Belleville, Chapter 4 of "High Performance Computing for Big Data: Methodologies & Applications", Chapman & Hall/CRC Press, Taylor and Francis Group, 2017.1, 320 pages.

PAPERS

[c23] Wei Wang (student), Vasilis Pavlidis, Yuanqing Cheng* (advisor), “Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wire-length”, accepted by 2020 ACM Great Lake Symposium on VLSI, 2020.

[c22] Jiacheng Ni (student), Xiaochen Guo and Yuanqing Cheng* (advisor), ”SIP: Boosting Up Graph Computing by Separating the Irregular Property Data”, accepted by 2020 ACM Great Lake Symposium on VLSI, Beijing China.

[c21] Jinbo Chen (student), Keren Liu, Xiaochen Guo, Patrick Girard and Yuanqing Cheng* (advisor), “DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache”, IEEE/ACM International Symposium on Quality Electronic Devices (ISQED), Santa Clara, CA, USA, March 25-26, 2020.

[j14] Jiacheng Ni (student), Keren Liu, Xiaolong Zhang, Bi Wu, Weisheng Zhao, Ying Wang, Yuanqing Cheng* (advisor), “Write back energy optimization for STT-MRAM based last level cache with data pattern characterization”, ACM Journal on Emerging Technologies in Computing Systems, 2020 (accepted).

[j13] Bi Wu, Beibei Zhang, Yuanqing Cheng*, Ying Wang, Dijun Liu, and Weisheng Zhao, "An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 8, 2019.

[j12] Bi Wu, Pengcheng Dai, Yuanqing Cheng*, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, and Weisheng Zhao, "A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs with Thermal Consideration", IEEE Transactions on Computer-Aided Design Integrated Circuits and Systems, vol. 39, no. 4, pp. 803-815, 2020.

[c20] Bi Wu, Xiaolong Zhang, Yuanqing Cheng*, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao, "Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization", IEEE Computer Society International Symposium on VLSI (ISVLSI), Hong Kong, China, July, 2018, pp. 333-338.

[c19] Bi Wu, Beibei Zhang, Yuanqing Cheng*, Ying Wang, Dijun Liu, Aida Todri-Sanial and Weisheng Zhao, "Chameleon: A Thermally Adaptive Error Correction Code Design for STT-MRAM LLCs", to appear on IEEE/ACM Design Automation Conference (DAC) WIP session, San Francisco, CA, USA, Jun. 2018.

[j11] Liuyang Zhang, Yuanqing Cheng, Wang Kang, Lionel Torres, Zhangyouguang, Aida Todri-Sanial and Weisheng Zhao, "Addressing the Thermal Issues of STT-MRAM from Compact Modeling to Design Techniques", IEEE Transactions on Nanotechnology, vol. 17, no. 2, pp. 345-352, 2018.

[c18] Chen Liu, Yuanqing Cheng*, Ying Wang, Youguang Zhang and Weisheng Zhao, "NEAR: a Novel Energy Aware Replacement Policy for STT-MRAM LLCs", in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May, 2018, pp. 1-4.

[j10]  Yinglin Zhao, Yuanqing Cheng*, Jianlei Yang, Weisheng Zhao and Aida Todri-Sanial, "Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint", Journal of Computer Science and Technology (JCST), Springer, vol. 33, no. 5, pp. 966-983 2018.

[j9] Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng*, Peiyuan Wang, Chando Park, Jimmy Kan, Seung H.Kang and Yuan Xie, "An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM based LLCs", IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 26, no. 3, pp. 484-495, 2018. 

[c17] Bi Wu, Yuanqing Cheng*, Pengcheng Dai, Jianlei Yang, Youguang Zhang，Dijun Liu, Ying Wang and Weisheng Zhao, "Thermosiphon: A Thermal Aware NUCA Architecture for Write Energy Reduction of the STT-MRAM based LLCs", in Proceedings of International Symopsium on Computer Aided Design (ICCAD), Irvine, CA, USA, Nov. 2017, pp. 474-481.

[j8] Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng and Xiaowei Li, "STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator", IEEE Transactions on Very Large Scale Integrated Systems vol. 25, no. 4, pp. 1285-1296, 2017.

[c16] Liu Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng and Yuan Xie, "Building energy-efficient multi-level cell STT-RAM caches with data compression", in Proceedings of Asian & South Pacific Design Automation Conference (ASP-DAC), Chiba/Tokyo, Japan, Jan. 2017, pp. 751-756.

[j7] Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng and Xiaowei Li, "PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM". IEEE Transactions on Very Large Scale Integrated Systems, vol. 24, no. 5, pp. 1613-1625, 2016.

[j6] Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen and Hai (Helen) Li, "Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach". IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 35, no. 3, pp. 380-393, 2016.

[c15] Liting Yu, Xiaoxiao Wang, Yuanqing Cheng, Xiaoying Zhao, Pengyuan Jiao, Aixin Chen, Donglin Su, LeRoy Winemberg, Mehdi Sadi and Mark Mohammad Tehranipoor, "An efficient all-digital IR-Drop Alarmer for DVFS-based SoC", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 221-224.

[c14] Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, Yuanqing Cheng* and Weisheng Zhao, "Quantitative evaluation of reliability and performance for STT-MRAM", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1150-1153.

[c13] Liang Wu, Xiaoxiao Wang, Xiaoying Zhao, Yuanqing Cheng, Donglin Su, Aixin Chen, Qihang Shi and Mark Tehranipoor, "AES design improvement towards information safety", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1706-1709.

[j5] Bi Wu, Yuanqing Cheng*, Jianlei Yang, Aida Todri-Sanial and Weisheng Zhao,
"Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM", IEEE Transactions on Reliability, vol. 65, no. 4, pp. 1755-1768, 2016.

[c12] Linuo Xue, Yuanqing Cheng*, Jianlei Yang, Peiyuan Wang and Yuan Xie, "ODESY: A novel 3T-3MTJ cell design with Optimized area DEnsity, Scalability and latency", in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), Austin, TX, USA, Nov. 2016, pp. 1-8.

[j4] Aida Todri-Sanial and Yuanqing Cheng, "A Study of 3-D Power Delivery Networks With Multiple Clock Domains", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 11, pp. 3218-3231, 2016.

[c11] Ping Chi, Shuangchen Li, Yuanqing Cheng, Yv Lu, S. H. Kang and Yuan Xie, "Architecture Design with STT-RAM: Opportunities and Challenges", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 2016, pp.109-114.

[j3] Yuanqing Cheng*, Aida Todri-Sanial, Jianlei Yang and Weisheng Zhao, "Alleviating Through Silicon Via Electromigration for Three-dimensional Integrated Circuits Taking Advantage of Self-healing Effect", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 11, pp. 3310-3322, 2016.

[c10] Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li and Xiaowei Li, "A case of precision-tunable STT-RAM memory design for approximate neural network", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1534-1537.

[c9] Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein and Weisheng Zhao, "Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM", in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, Jul. 2015, pp. 461-466.

[c8] Bi Wu, Yuanqing Cheng*, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres and Weisheng Zhao, "An architecture-level cache simulation framework supporting advanced PMA STT-MRAM", in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Boston, MA, USA, Jul. 2015, pp. 7-12.

[c7] Xiaolong Zhang, Yuanqing Cheng*, Ying Wang, Weisheng Zhao and Aida Todri-Sanial, "Write back energy optimization for STT-RAM based cache using data pattern characterization", IEEE/ACM Design Automation Conference (DAC) WIP session, San Francisco, CA, USA, Jun. 2015.

[c6] Lun Yang, Yuanqing Cheng*, Ying Wang, Hao Yu, Weisheng Zhao and Aida Todri-Sanial, "A body-biasing of readout circuit for STT-RAM with improved thermal reliability", in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1530-1533.

[c5] Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng and Xiaowei Li, "HARS: A High-Performance Reliable Routing Scheme for 3D NoCs", in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, USA, Jul. 2014, pp. 392-397.

[c4] Xiaolong Zhang, Yuanqing Cheng*, Weisheng Zhao, Youguang Zhang and Aida Todri-Sanial, "Exploring Potentials of Perpendicular Magnetic Anisotropy STT-MRAM for Cache Design", in Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China, Oct. 2014, pp. 893-895.

[c3] Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, and Arnaud Virazel, "Power Supply Noise-Aware Workload Assignments for Homogenous 3D MPSoCs with Thermal Consideration", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, Jan. 2014, pp.544-549.

[j2] Yuanqing Cheng, Lei Zhang, Yinhe Han, and Xiaowei Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 21, no. 2, pp. 239-249, 2013.

[j1] Yuanqing Cheng, Lei Zhang, Yinhe Han, and Xiaowei Li, "TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design", Journal of Computer Science and Technology (JCST), vol. 28, no. 1, pp. 119-128, 2013.

[c2] Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vevet and Marc Belleville, "A novel method to mitigate TSV electromigration for 3D ICs", in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Natal, Brazil, Jul. 2013, pp. 121-126.

[c1] Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu and Xiaowei Li, "Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC", in Proceedings of IEEE Asian Test Symposium (ATS), New Delhi, India, Nov. 2011, pp. 181-186.