Research @ CADET Lab.

1. Low Power & Physical Design of Monolithic 3D Integrated Circuits

As the semiconductor technology node advances, interconnect delay and power consumption have dominated the total chip performance and power budget. In order to deal with this challenge, 3D integrated circuit technology was proposed in the last decade. 

In this research direction, we manage to explore the 3D integrated circuit technology to reduce the chip power consumption and alleviate thermal issue induced by 3D integration. Both TSV-based and emerging monolithic 3D IC technologies are considered in our research. 

This research topic is supported by Natural Science Foundation China under grant No. 61401008.

2. STT-MARM Based Computer Architecture Design & Optimizations

Moore's law predicts the exponential increase of integration density of semiconductor devices on chip. At the same time, processor performance improves thanks to the shrinking technology node. Off-chip memory bandwidth, however, can not sustain the same developing speed and become the new bottleneck for system performance improvement. Therefore, it requires to enlarge on-chip cache capacity. 

Traditional SRAM-based cache has several drawbacks, e.g., large cell area, high leakage power, etc. STT-MRAM utilizes MTJ (magneto tunneling junction) to store data. Compared to charge-based storage media, like SRAM or DRAM, it has several promising merits, such as high integration density, non-volatility and ultra-low leakage power. 

In this research direction, we explore the opportunities to use STT-MRAM as last level cache and manage to optimize the computer architecture design to dig the full potential of STT-MARM. We also investigate the reliability issue, especially the impact of PVT variations on STT-MRAM operations. 

This research direction is supported by National Natural Science Foundation China under grand No. 61401008, Beijing Natural Science Foundation under grant No. 4154076, Beijing Natural Science Foundation under grant No. 4192035, and the State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS.

3. Carbon-nano Tube Based Circuit & Computer Architecture Design

CNT-based FET and Interconnect has drawn enormous attentions recently. To approach high data processing ability for exascale computing, carbon nanotube (CNT) device emerges due to impressive performance improvement and power efficiency compared to the CMOS counterpart. CNT-FET (carbon nanotube transistor) has superior scaling ability and could be used for high speed data computing. 

We will develop CNT interconnect electrical and thermal analytical models that can be used for circuitand system-level simulation. We will perform in-depth simulations for assessing the performance of circuits when fine CNT lines are used as local interconnects. Similarly, we will perform system-level simulations for assessing the performance of composite Cu -CNT interconnect lines as global interconnects. We will explore composite Cu-CNT interconnect lines for power, clock and signal interconnects where figure of merits such as delay, power, thermal and signal integrity will be evaluated. 

CNT is a promising material of transistor devices because of its superior power efficiency and high performance. In order to evaluate the benefits brought by this emerging technology, we need to develop CNT-FET device compact model for SPICE simulation. The model could capture the electrical behavior of CNT-FET and be validated by experimental measurements. Based on the device model, we will build primitive logic gates and develop the CNT-FET based standard cell library for CNT logic design. With the help of cell library, we could evaluate the benefits of CNT logic circuits (e.g. full adder, multiplier, etc.) compared to the CMOS counterparts in terms of performance, area and power consumption.

This research topic is supported by Programs for Foreign Talents, Beihang University under grant No. Z2018004.