Greate Ideas in Computer Architecture, Fall 2020

 

Syllabus

This course introduces the principles involved in designing a modern microprocessor and the working mechanism of a modern computing system, such like instruction set architecture, data path/control path design, memory hierarchy, I/O system, parallel processing and the preliminaries of classic MIPS instruction set architecture released by Stanford University. All the teaching materials are also based on those of CS61C in U.C., Berkeley. Thanks a lot for UCB colleagues to make this course a wonderful adventure in computer architecture world! Special thanks to Prof. Dan Garcia and Prof. David Patterson.

Textbooks

textbook_cover

Annoucements

[2020/09/07] The classroom is 主401, Xueyuan Rd. Campus. Welcome to this course!

Schedule

Lectures Date Lecture Topic Reading Lab Homework Project
1-1
 2020/09/07 Course Introduction 1  

 

  
1-2
 2020/09/07 Number Representation 3.1, 3.2 (exclude Fig. 3.1) IMD1   1.1-1.28,1.28-1.45,1.50, 1.59  
2-1
 2020/09/11 MIPS Intro 2.1-2.3
FMP3
  3.2 3.4 3.6 3.8 
2-2
 2020/09/11 MIPS lw, sw, Decisions I 2.6-2.9
AppA
FMP2
  2.1 2.2 2.5 2.6 
3-1
 2020/09/14 MIPS Decisions II 2.7, 2.9 , A.6
IMD2-Jump-Tables
IMD2-Tail-Recursion
Lab1
lab1_ex1.s
lab1_ex3.s
lab1_ex4.c
 2.10, 2.11, 2.13,2.14 
3-2
 2020/09/14 MIPS Procedures I 2.7, A.6
   2.15, 2.16, 2.21, 2.29   
4-1
 2020/09/18 MIPS Procedures & Logic Ops 3.3, 2.5
      
4-2
 2020/09/18 MIPS Instruction Format I 2.4, 2.9
        
5-1
 2020/09/21 MIPS Instruction Format II 2.4, 2.9
        
5-2
 2020/09/21 Floating Point I 3.4, 3.5, 3.6, 3.8
        
6-1
 2020/09/25 Floating Point II 3.10
   3.1, 3.4, 3.7, 3.9， 3.14， 3.32， 3.37， 3.45    
6-2
 2020/09/25 MIPS Instruction Format III          
7-1
 2020/09/28 Compilation, Assembly, Linking I 2.10, A.1-A.4        
7-2
 2020/09/28 Compilation, Assembly, Linking II   Lab2
p2.s
      
8-1
 2020/10/09 Intro to Synch. Digital systems SDS Handout      
8-2
 2020/10/09 State Elements B.3-B.6 State Handout        
9-1
 2020/10/12 Introduction to Combinational Logic B.2-B.3 Logic Handout
B.2, B.4, B.6, B.11, B.18, B.21 IMDB
FMPB 		    
9-2
 2020/10/12 Combinational Logic Blocks B.2-B.3 Blocks Handout
App. B
        
10-1
 2020/10/16 Intro to CPU Design        

 

 
10-2
 2020/10/16 CPU Design: Single-Cycle I 5.3        
11-1
 2020/10/16 CPU Design: Single-Cycle II 5.4 Lab3      
11-2
 2020/10/16 CPU Design: Control 5.4        
12-1&2
 2020/10/16 CPU Design: Pipelining I P&H (3rd): 6.1-6.3   5.1， 5.2， 5.5， 5.8， 5.11，5.14，5.25    
13-1
 2020/10/16 CPU Design: Pipelining II P&H (3rd): 6.4-6.6          
13-2
 2020/10/16 Caches I P&H (3rd): 7.1        
14-1
 2020/10/30 Caches II P&H (3rd): 7.2      
14-2
 2020/10/30 Caches II P&H (3rd): 7.2        
15-1
 2020/11/2 Caches III P&H (3rd): 7.3
IMD7
   7.1 7.3 7.6 7.11 7.25 7.32 7.36
FMP7
   
15-2
 2020/11/2 Virtual Memory I P&H (3rd): 7.3-7.8        
16-1
 2020/11/2 Virtual Memory II P&H (3rd): 7.3-7.8        
16-2
 2020/11/2 I/O: Basics, Storage, & Networks P&H (3rd): 8.1-8.3        

 

Instructor

Prof. Yuanqing Cheng from School of Microelectronics, Beihang University.